1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a sense amplifier (hereinafter referred to as SA) which operates when multiple bits are read out at the same time from memory cells connected to a word line (hereinafter referred to as W line).
2. Description of Related Art
Some memory products require to read out multiple bits at the same time. In such memory products, if cells to be read out are connected to the same W line, SAs of the number of the bits operates simultaneously. The power consumption at this time (operating power of the SAs) must be reduced. Reducing the power consumption is important especially at a parallel output of multiple bits.
Soft error measures at the time of simultaneous read-out of memory cells connected to one W line is required as a technique concerning the simultaneous read-out of multiple bits. Especially important is measures to 2-bit errors that cannot be corrected by a normal ECC (Error Checking and Correcting) circuit.
An operation of SA according to related arts when outputting multiple cells at the same time, which are connected to one W line, is disclosed in Japanese Unexamined Patent Application Publication Nos. 2003-272390 (Honda), 2007-157283 (Shimada), and 62-150590 (Miyazawa). The technique disclosed by Honda divides cells into multiple groups to form multiple SA groups. These SA groups do not start operating at the same time but start operating at different time from each other. This enables to reduce the peak current when the SAs are operating.
The technique disclosed by Shimada also divides cells into multiple SA groups and shifts operation timings of the SA groups according to clocks. This enables to reduce the peak current when the SAs are operating. The technique disclosed by Miyazawa divides cells into multiple SA groups and arranges them so that the SA groups not operating simultaneously are connected to a common W line by an appropriate layout spatially and temporally.
As a normal ECC circuit, 1-bit error correcting and 2-bit error detecting circuit is used. This is referred to as a an SEC-DED (Single Error Correction-Double Error Detection). Measures to an error of 2 bits or more which cannot be corrected in the ECC circuit are disclosed by Japanese Unexamined Patent Application Publication No. 2003-077294 (Hatanaka et al). The technique disclosed by Hatanaka et al. divides ECC circuits into multiple groups so that data from memory cells (SA output) connected to each ECC circuit group become data of every three cells. There is extremely small possibility that two cells which are 4 cells away from each other are erroneous simultaneously. Thus the ECC circuit may only be a normal ECC circuit which can correct 1-bit error in substance. However, in the technique disclosed by Hatanaka et al., SAs do not divide the cells.
In the relates arts disclosed by Honda, Shimada, and Miyazawa, the SA groups are not started to operate simultaneously, thereby enabling to suppress the current from flowing at the same time as the SA groups start to operate. However, there is a time zone when multiple SA groups are operating simultaneously. In this document, this time zone is referred to as stable operation time to differentiate from operation start time.
In the stable operation time shown in FIG. 2 for Honda, t1′ to t2′ in FIG. 2 for Shimada, and FIG. 4 for Miyazawa, multiple SA groups are operating at the same time. Such techniques prevent a large current as at the operation start time from flowing, however currents still flows in each SA group. The related arts do not see a problem in the current value when multiple SA groups are operating simultaneously (at the stable operation time, not the operation start time for SA group). If there are not many SA groups, the operation start time of the SA groups can be shifted so that there is no problem in the current at the stable operation time when the SA groups are operating.
However, in the case of reading out 100 bits (100 SAs for DRAM) at the same time, the current at the stable operation time is non-negligible in which many SA groups are operating simultaneously, although it depends on how many of SA groups are divided into a group. That is, it is not a problem even if a few SA groups are operating simultaneously at the stable operation time. However if the SA groups increase from 4 to 8, superimposed current at the stable operation time is non-negligible in which multiple SA groups are operating simultaneously
FIG. 4 shows a circuit diagram of a memory array according to a related art. 128 cells are connected to one W line as shown in FIG. 4. Each SA is connected to respective bit line. The SAs are activated in response to an SA activation signal SE. Further, a particular bit line is selected by a bit line selection signal YSW, read-out data from a cell amplified by the SA is transmitted to a Local I/O bus, and the read-out data is input to a data amplifier (DAMP).
FIG. 5 shows an operation timing chart of a memory array of FIG. 4. As shown in FIG. 5, an SA is activated by an activation signal SE. Then a bit line is selected by a bit line selection signal YSW. A current for charging and discharging the bit line is consumed immediately after activating the SA. After the bit line selection signal YSW is released, the Local I/O bus is charged and discharged. As the memory capacity increases, the load capacity of this Local I/O bus also increases, thereby increasing the period in which the charging and discharging current flows.